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DTSTART:19700308T020000
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DTSTAMP:20200129T163601Z
LOCATION:607
DTSTART;TZID=America/Denver:20191117T114500
DTEND;TZID=America/Denver:20191117T121000
UID:submissions.supercomputing.org_SC19_sess110_ws_h2rc103@linklings.com
SUMMARY:The Memory Controller Wall: Benchmarking the Intel FPGA SDK for Op
 enCL Memory Interface
DESCRIPTION:Workshop\n\nThe Memory Controller Wall: Benchmarking the Intel
  FPGA SDK for OpenCL Memory Interface\n\nZohouri, Matsuoka\n\nSupported by
  their high power efficiency and recent advancements in High Level Synthes
 is (HLS), FPGAs are quickly finding their way into HPC and cloud systems. 
 Large amounts of work have been done so far on loop and area optimizations
  for different applications on FPGAs using HLS. However, a comprehensive a
 nalysis of the behavior and efficiency of the memory controller of FPGAs i
 s missing in literature, which becomes even more crucial when the limited 
 memory bandwidth of modern FPGAs compared to their GPU counterparts is tak
 en into account. In this work, we will analyze the memory interface genera
 ted by Intel FPGA SDK for OpenCL with different configurations for input/o
 utput arrays, vector size, interleaving, kernel programming model, on-chip
  channels, operating frequency, padding, and multiple types of overlapped 
 blocking. Our results point to multiple shortcomings in the memory control
 ler of Intel FPGAs, especially with respect to memory access alignment, th
 at can hinder the programmer’s ability in maximizing memory performance in
  their design. For some of these cases, we will provide work-arounds to im
 prove memory bandwidth efficiency; however, a general solution will requir
 e major changes in the memory controller itself.\n\nTag: Workshop Reg Pass
 , Accelerators, Compilers, FPGA, Quantum Computing, Reconfigurable Computi
 ng\n\nRegistration Category: Workshop Reg Pass, Accelerators, Compilers, F
 PGA, Quantum Computing, Reconfigurable Computing
URL:https://sc19.supercomputing.org/presentation/?id=ws_h2rc103&sess=sess1
 10
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