BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Denver
X-LIC-LOCATION:America/Denver
BEGIN:DAYLIGHT
TZOFFSETFROM:-0700
TZOFFSETTO:-0600
TZNAME:MDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0600
TZOFFSETTO:-0700
TZNAME:MST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20200129T163601Z
LOCATION:607
DTSTART;TZID=America/Denver:20191117T155500
DTEND;TZID=America/Denver:20191117T162000
UID:submissions.supercomputing.org_SC19_sess110_ws_h2rc109@linklings.com
SUMMARY:Implementation and Impact of an Ultra-Compact Multi-FPGA Board for
  Large System Prototyping
DESCRIPTION:Workshop\n\nImplementation and Impact of an Ultra-Compact Mult
 i-FPGA Board for Large System Prototyping\n\nChaix, Ioannou, Kossifidis, D
 imou, Ieronymakis...\n\nEfficient prototyping of a large complex system ca
 n be significantly facilitated by the use of a flexible and versatile phys
 ical platform where both new hardware and software components can readily 
 be implemented and tightly integrated in a timely manner. Towards this end
 , we have developed the 120130 mm QFDB board and associated firmware, inc
 luding the system software environment. We developed a large system based 
 on this advanced dense and modular building block. The QFDB features 4 int
 erconnected Xilinx Zynq Ultrascale+ devices, each one consisting of an ARM
 -based subsystem tightly coupled with reconfigurable logic. Each Zynq Ultr
 ascale+ is connected to 16 GB of DDR4 memory. In addition, one Zynq provid
 es storage through an M.2 Solid State Disk (SSD). In this paper, we presen
 t the design and the implementation of this board, as well as the software
  environment for board operation. Moreover, we describe a 10 Gb Ethernet c
 ommunication infrastructure for interconnecting multiple boards together. 
 Finally, we highlight the impact of this board on a number of ongoing rese
 arch activities that leverage the QFDB versatility, both as a large scale 
 prototyping system for HPC solutions, and as a host for the development of
  FPGA integration techniques.\n\nTag: Workshop Reg Pass, Accelerators, Com
 pilers, FPGA, Quantum Computing, Reconfigurable Computing\n\nRegistration 
 Category: Workshop Reg Pass, Accelerators, Compilers, FPGA, Quantum Comput
 ing, Reconfigurable Computing
URL:https://sc19.supercomputing.org/presentation/?id=ws_h2rc109&sess=sess1
 10
END:VEVENT
END:VCALENDAR