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DTSTART:19700308T020000
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DTSTAMP:20200129T163601Z
LOCATION:607
DTSTART;TZID=America/Denver:20191117T164000
DTEND;TZID=America/Denver:20191117T170500
UID:submissions.supercomputing.org_SC19_sess110_ws_h2rc110@linklings.com
SUMMARY:Combining Perfect Shuffle and Bitonic Networks for Efficient Quant
 um Sorting
DESCRIPTION:Workshop\n\nCombining Perfect Shuffle and Bitonic Networks for
  Efficient Quantum Sorting\n\nMahmud, Srimoungchanh, Haase-Divine, Blanken
 au, Kuhnke...\n\nThe emergence of quantum computers in the last decade has
  generated research interest in applications such as quantum sorting. Quan
 tum sorting plays a critical role in creating ordered sets of data that ca
 n be better utilized, e.g., quantum ordered search or quantum network swit
 ching.  In this paper, we propose a quantum sorting algorithm that combine
 s highly parallelizable bitonic merge networks with perfect shuffle permut
 ations (PSP), for sorting data represented in the quantum domain. The comb
 ination of bitonic networks with PSP improves the temporal complexity of b
 itonic merge sorting which is critical for reducing decoherence effects fo
 r quantum processing. We present space-efficient quantum circuits that can
  be used for quantum bit comparison and permutation.  We also present a re
 configurable hardware quantum emulator for prototyping the proposed quantu
 m algorithm. The emulator has a fully-pipelined architecture and supports 
 double-precision floating-point computations, resulting in high throughput
  and accuracy. The proposed hardware architectures are implemented on a hi
 gh-performance reconfigurable computer (HPRC). In our experiments, we emul
 ated quantum sorting circuits of up to 31 fully-entangled quantum bits on 
 a single FPGA node of the HPRC platform. To the best of our knowledge, our
  effort is the first to investigate a reconfigurable hardware emulation of
  quantum sorting using bitonic networks and perfect shuffle.\n\nTag: Works
 hop Reg Pass, Accelerators, Compilers, FPGA, Quantum Computing, Reconfigur
 able Computing\n\nRegistration Category: Workshop Reg Pass, Accelerators, 
 Compilers, FPGA, Quantum Computing, Reconfigurable Computing
URL:https://sc19.supercomputing.org/presentation/?id=ws_h2rc110&sess=sess1
 10
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