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DTSTART:19700308T020000
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DTSTAMP:20200129T163601Z
LOCATION:607
DTSTART;TZID=America/Denver:20191117T103000
DTEND;TZID=America/Denver:20191117T104500
UID:submissions.supercomputing.org_SC19_sess110_ws_h2rc119@linklings.com
SUMMARY:2GRVI Phalanx: A 1332-Core RISC-V RV64I Processor Cluster Array wi
 th an HBM2 High Bandwidth Memory System, and an OpenCL-like Programming Mo
 del, in a Xilinx VU37P FPGA [WIP Report]
DESCRIPTION:Workshop\n\n2GRVI Phalanx: A 1332-Core RISC-V RV64I Processor 
 Cluster Array with an HBM2 High Bandwidth Memory System, and an OpenCL-lik
 e Programming Model, in a Xilinx VU37P FPGA [WIP Report]\n\nGray\n\n2GRVI 
 (and its predecessor, GRVI) are FPGA-efficient 64b (resp. 32b) RISC-V proc
 essing element cores. Phalanx is a parallel processor and accelerator arra
 y overlay framework. Groups of PEs and accelerator cores form shared memor
 y compute clusters. Clusters, DRAM, NICs and other I/O controllers communi
 cate by message passing on an FPGA-optimal Hoplite torus soft NoC. This ex
 tended abstract summarizes work-in-progress to redesign the 2017 GRVI Phal
 anx to take advantage of new Xilinx FPGAs with 460 GB/s dual stack HBM2 DR
 AM-in-package, and to provide a familiar parallel programming experience v
 ia an OpenCL-like programming model and tools. The new system is the first
  kilocore RV64I SoC and the first RISC-V multiprocessor with an HBM2 memor
 y system.\n\nTag: Workshop Reg Pass, Accelerators, Compilers, FPGA, Quantu
 m Computing, Reconfigurable Computing\n\nRegistration Category: Workshop R
 eg Pass, Accelerators, Compilers, FPGA, Quantum Computing, Reconfigurable 
 Computing
URL:https://sc19.supercomputing.org/presentation/?id=ws_h2rc119&sess=sess1
 10
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