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DTSTART:19700308T020000
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DTSTAMP:20200129T163601Z
LOCATION:607
DTSTART;TZID=America/Denver:20191117T121000
DTEND;TZID=America/Denver:20191117T123000
UID:submissions.supercomputing.org_SC19_sess110_ws_h2rc121@linklings.com
SUMMARY:Accelerating Large Garbled Circuits on an FPGA-Enabled Cloud
DESCRIPTION:Workshop\n\nAccelerating Large Garbled Circuits on an FPGA-Ena
 bled Cloud\n\nLeeser, Gungor, Huang, Ioannidis\n\nGarbled Circuits (GC) is
  a technique for ensuring the privacy of inputs from users and is particul
 arly well suited for FPGA implementations in the cloud where data analytic
 s is frequently run. Secure Function Evaluation, such as that enabled by G
 C, is orders of magnitude slower than processing in the clear. We present 
 our best implementation of GC on Amazon Web Services (AWS) that implements
  garbling on Amazon’s FPGA enabled F1 instances. In this paper we present 
 the largest problems garbled to date on FPGA instances, which includes pro
 blems that are represented by over four million gates. Our implementation 
 speeds up garbling 20 times over software over a range of different circui
 t sizes.\n\nTag: Workshop Reg Pass, Accelerators, Compilers, FPGA, Quantum
  Computing, Reconfigurable Computing\n\nRegistration Category: Workshop Re
 g Pass, Accelerators, Compilers, FPGA, Quantum Computing, Reconfigurable C
 omputing
URL:https://sc19.supercomputing.org/presentation/?id=ws_h2rc121&sess=sess1
 10
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