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DTSTART:19700308T020000
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LOCATION:704-706
DTSTART;TZID=America/Denver:20191117T110000
DTEND;TZID=America/Denver:20191117T113000
UID:submissions.supercomputing.org_SC19_sess114_ws_prot103@linklings.com
SUMMARY:Asvie: A Timing-Agnostic SVE Optimization Methodology
DESCRIPTION:Workshop\n\nAsvie: A Timing-Agnostic SVE Optimization Methodol
 ogy\n\nTairum Cruz, Ruiz, Rusitoru\n\nAs we are quickly approaching exasca
 le and moving onwards towards the next challenge, we are exploring a wider
  range of technologies and architectures. The further out the timeframes c
 onsidered, the less likely prototype hardware is available. A popular meth
 od of exploring new architectural extensions is to emulate them on existin
 g platforms. The Arm Instruction Emulator (ArmIE) is such a tool, which we
  use on existing Armv8 platforms to run Arm's latest vector architecture, 
 the Scalable Vector Extension (SVE).\n\nTo aid with porting applications t
 owards SVE, we developed an application optimization methodology based on 
 ArmIE that uses timing-agnostic metrics to assess application quality. We 
 show how we have successfully optimized the High Performance Conjugate Gra
 dient (HPCG) High Performance Computing benchmark to SVE by using our meth
 odology, resulting in a hand-optimized intrinsics-based version.\n\nTag: W
 orkshop Reg Pass, Performance, Programming Systems, Visualization\n\nRegis
 tration Category: Workshop Reg Pass, Performance, Programming Systems, Vis
 ualization
URL:https://sc19.supercomputing.org/presentation/?id=ws_prot103&sess=sess1
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