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DTSTART;TZID=America/Denver:20191118T142200
DTEND;TZID=America/Denver:20191118T144100
UID:submissions.supercomputing.org_SC19_sess117_ws_mchpc112@linklings.com
SUMMARY:Explicit Data Layout Management for Autotuning Exploration on Comp
 lex Memory Topologies
DESCRIPTION:Workshop\n\nExplicit Data Layout Management for Autotuning Exp
 loration on Complex Memory Topologies\n\nPerarnau, Videau, Denoyelle, Monn
 a, Iskra...\n\nThe memory topology of high-performance computing platforms
  is becoming more\ncomplex. Future exascale platforms in particular are ex
 pected to\nfeature multiple types of memory technologies, and multiple acc
 elerator\ndevices per compute node.\n\nIn this paper, we discuss the use o
 f explicit management of the layout of data\nin memory across memory nodes
  and devices for performance exploration purposes.\nIndeed, many classic o
 ptimization techniques rely on reshaping or tiling input\ndata in specific
  ways to achieve peak efficiency on a given architecture.\n\nWith autotuni
 ng of a linear algebra code as the end goal, we present AML:  a framework\
 nto treat three memory management abstractions as first-class citizens: da
 ta\nlayout in memory, tiling of data for parallelism, and data movement ac
 ross\nmemory types. By providing access to these abstractions as part\nof 
 the performance exploration design space, our framework eases the design a
 nd\nvalidation of complex, efficient algorithms for heterogeneous platform
 s.\n\nUsing the Intel Knights Landing architecture in one of its most NUMA
 \nconfigurations as a proxy platform, we showcase our framework by\nexplor
 ing tiling and prefetching schemes for a DGEMM algorithm.\n\nTag: Workshop
  Reg Pass, HPC, Memory, OS and Runtime Systems, Runtime Systems\n\nRegistr
 ation Category: Workshop Reg Pass, HPC, Memory, OS and Runtime Systems, Ru
 ntime Systems
URL:https://sc19.supercomputing.org/presentation/?id=ws_mchpc112&sess=sess
 117
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