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DTSTAMP:20200129T163557Z
LOCATION:603
DTSTART;TZID=America/Denver:20191118T091000
DTEND;TZID=America/Denver:20191118T093000
UID:submissions.supercomputing.org_SC19_sess122_ws_pmbss104@linklings.com
SUMMARY:Automatic Throughput and Critical Path Analysis of x86 and ARM Ass
 embly Kernels
DESCRIPTION:Workshop\n\nAutomatic Throughput and Critical Path Analysis of
  x86 and ARM Assembly Kernels\n\nLaukemann, Hammer, Hager, Wellein\n\nUsef
 ul models of loop kernel runtimes on out-of-order architectures require an
  analysis of the in-core performance behavior of instructions and their de
 pendencies. While an instruction throughput prediction sets a lower bound 
 to the kernel runtime, the critical path defines an upper bound. Such pred
 ictions are an essential part of analytic (i.e., white-box) performance mo
 dels like the Roofline and Execution-Cache-Memory (ECM) models. They enabl
 e  a better understanding of the performance-relevant interactions between
  hardware architecture and loop code.\n\nThe Open Source Architecture Code
  Analyzer (OSACA) is a static analysis tool for predicting the execution t
 ime of sequential loops. It previously supported only x86 (Intel and AMD) 
 architectures and simple, optimistic full-throughput execution. We have he
 avily extended OSACA to support ARM instructions and critical path predict
 ion including the detection of loop-carried dependencies, which turns it i
 nto a versatile cross-architecture modeling tool. We show runtime predicti
 ons for code on Intel Cascade Lake, AMD Zen, and Marvell ThunderX2 micro-a
 rchitectures based on machine models from available documentation and semi
 -automatic benchmarking. The predictions are compared with actual measurem
 ents.\n\nTag: Workshop Reg Pass, Benchmarks, Performance, Scientific Compu
 ting, Simulation\n\nRegistration Category: Workshop Reg Pass, Benchmarks, 
 Performance, Scientific Computing, Simulation
URL:https://sc19.supercomputing.org/presentation/?id=ws_pmbss104&sess=sess
 122
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