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LOCATION:710
DTSTART;TZID=America/Denver:20191118T103000
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UID:submissions.supercomputing.org_SC19_sess125_pec254@linklings.com
SUMMARY:HPC Interconnects at the End of Moore’s Law
DESCRIPTION:Workshop\n\nHPC Interconnects at the End of Moore’s Law\n\nSha
 lf\n\nThe tapering of lithography advances that have been associated with 
 Moore’s Law will substantially change requirements for future interconnect
  architectures for large-scale datacenters and HPC systems. Architectural 
 specialization is creating new datacenter requirements such as emerging ac
 celerator technologies for machine learning workloads and rack disaggregat
 ion strategies will push the limits of current interconnect technologies. 
 Whereas photonic technologies are often sold on the basis of higher bandwi
 dth and energy efficiency (e.g. lower picojoules per bit), these emerging 
 workloads and technology trends will shift the emphasis to other metrics s
 uch as bandwidth density (as opposed to bandwidth alone) and reduced laten
 cy, and performance consistency. Such metrics cannot be accomplished with 
 device improvements alone, but require a systems view of photonics in data
 centers.\n\nTag: Workshop Reg Pass, Architectures, Datacenter, Emerging Te
 chnologies, Hardware, HPC, I/O, Networks, Photonics, Silicon Fabrication\n
 \nRegistration Category: Workshop Reg Pass, Architectures, Datacenter, Eme
 rging Technologies, Hardware, HPC, I/O, Networks, Photonics, Silicon Fabri
 cation
URL:https://sc19.supercomputing.org/presentation/?id=pec254&sess=sess125
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