Dr. Cesarini graduated in Computer Engineering from the University of Bologna in 2014, where he also earned a Ph.D. degree in Electrical Engineering from the Department of Electrical, Electronic and Information Engineering in 2019. He is currently an HPC software engineer at CINECA, the Italian supercomputing center, where he works in code porting and performance optimization on large-scale scientific applications for the new generation of heterogeneous HPC architectures. His research interests also concern the development of SW-HW codesign strategies as well as algorithms for parallel programming support for energy-efficient HPC systems.
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