Workshop: H2RC 2019: Fifth International Workshop on Heterogeneous High-Performance Reconfigurable Computing
Event TypeWorkshop
Registration Categories
Quantum Computing
Reconfigurable Computing
TimeSunday, 17 November 20199am - 5:30pm
DescriptionAs in the previous four years, this workshop will bring together application experts, software developers, and hardware engineers, both from industry and academia, to share experiences and best practices to leverage the practical application of reconfigurable logic to Scientific Computing, Machine/Deep Learning, and “Big Data” applications. In particular, the workshop will focus on sharing experiences and techniques for accelerating applications and/or improving energy efficiency with FPGAs using OpenCL, OpenMP, OpenACC, SYCL, C, C++, and other high-level design flows, which enable and improve cross-platform functional and performance portability while also improving productivity. Particular emphasis is given to cross-platform comparisons and combinations that foster a better understanding within the industry and research community on what are the best mappings of applications to a diverse range of hardware architectures that are available today (e.g., FPGA, GPU, Many-cores and hybrid devices, ASICs), and on how to most effectively achieve cross-platform compatibility.
9:00am - 9:05amH2RC 2019: Fifth International Workshop on Heterogeneous High-Performance Reconfigurable Computing
9:05am - 9:45amSYCL: A Single-Source C++ Standard for Heterogeneous Computing
9:45am - 10:00amhlslib: Software Engineering for Hardware Design
10:00am - 10:30amMorning Coffee Break
10:30am - 10:45am2GRVI Phalanx: A 1332-Core RISC-V RV64I Processor Cluster Array with an HBM2 High Bandwidth Memory System, and an OpenCL-like Programming Model, in a Xilinx VU37P FPGA [WIP Report]
10:45am - 11:00amCFD Acceleration with FPGA
11:00am - 11:15amData Flow Pipes: A SYCL Extension for Spatial Architectures
11:15am - 11:20amMorning 5-Minute Break
11:20am - 11:45amIt's All about Data Movement: Optimizing FPGA Data Access to Boost Performance
11:45am - 12:10pmThe Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface
12:10pm - 12:30pmAccelerating Large Garbled Circuits on an FPGA-Enabled Cloud
12:30pm - 2:00pmH2RC'19 Lunch Break
2:00pm - 2:40pmML Acceleration with Heterogeneous Computing for Big Data Physics Experiments
2:40pm - 3:00pmTestbed for the Research Community Exploring Next-Generation Cloud Platforms
3:00pm - 3:30pmAfternoon Break
3:30pm - 3:55pmHigh-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud
3:55pm - 4:20pmImplementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping
4:20pm - 4:25pmAfternoon 5-Minute Break
4:25pm - 4:40pmFBLAS: Streaming Linear Algebra Kernels on FPGA
4:40pm - 5:05pmCombining Perfect Shuffle and Bitonic Networks for Efficient Quantum Sorting
5:05pm - 5:30pmPerformance and Energy Efficiency Analysis of Reverse Time Migration on a FPGA Platform
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